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| List of Groups
/ Simulation
(VLSI) Lab |
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| Group |
Simulation |
| Group
Leader |
V
Krishnamurthy, Senior Design Engineer |
| Email |
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Section - Simulation
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| Team
Members |
- V Krishnamurthy, Senior Design Engineer
- D Ramarao, Senior Design Engineer
- D S Raje, Senior Design Engineer
- Ms. P D Bharne, Asstt. Engineer
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| Area
of Expertise |
- Electronics Design Automation
- FPGA Design
- Circuit Miniaturization & Optimization
- VLSI Design
- Embedded Systems
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| Facilities |
- EDA Tools, both Front & Back end
- Digital & Analog Mixed Signal Design
Tools
- Board (PCB) Design, Analysis Tools
- FPGA, CPLD, Design Tools
- FPGA Demo Board
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| Tools
and Instruments |
- Cadence Tool on Digital & Analog Mixed
Signal Design
- Front & Back end capabilities
- HP Unix Platforms with Five Workstations
- Testing & Analyzing Tools, Logic Analyzer,
DSO, RF Spectrum Analyser, Modulation Analyzer
- Microcontroller (MCS-51) Kits, Universal
Programmer
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| Ongoing
Projects |
Miniaturization
of Auto-rickshaw Meter in VHDL |
| Courses
offered |
Short Term Courses
- VHDL for Digital Designers
- Circuit Simulation & Foundations for
Analog Chip Design
- Certificate Course in VLSI Design (Digital
Systems Design)
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| Facilities
planned in the near future |
Xi-Link-iste 6.3i
Altera Backend
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